1. Field of the Invention
This invention concerns an intermediate potential generation circuit for generating a potential intermediate between a power source potential Vcc and ground potential in a semiconductor chip, such as a LSI chip. More particularly, this invention concerns an intermediate potential generation circuit which has a large current driving capacity and a low power consumption.
2. Description of the Background
Conventionally, intermediate potential circuits as shown in FIGS. 1 (a) to (c) are used to generate an intermediate potential within a LSI chip.
In FIG. 1 (a), an intermediate potential VM is achieved at node 2 by dividing a power source potential Vcc supplied to a terminal 1 by resistors R1 and R2.
In FIG. 1 (b), an intermediate potential VM is achieved at node 4 by dividing a power source potential Vcc supplied to a terminal 3 by a resistor R3 and a series connection of diodes D1 to D3.
In FIG. 1 (c), the intermediate voltage VM is maintained within a range determined by the reference potentials at nodes N2 and N3. Namely, the potential VN2 at node N2 is higher than the potential VN1 at the node N1 by the threshold voltage VTN3 of an N-channel MOS transistor M3. Thus, the potential VN2 is expressed as follows. EQU VN2=VN1+VTN3 (1)
On the other hand, the potential VN3 at the node N3 is lower than the potential VN1 by the absolute value VTP4 of the threshold voltage of a P-channel MOS transistor M4. Thus, it is expressed as follows. EQU VN3=VN1-VTP4 (2)
In the case where the intermediate potential VM is lower than the first reference potential VN2 by the threshold voltage VTN1 of the N-channel MOS transistor M1, the MOS transistor M1 changes to a conductive state, and the intermediate potential VM is raised.
When the intermediate potential VM is higher than the second reference potential VN3 by the absolute value VTP2 of the threshold voltage of a P-channel MOS transistor M2, the MOS transistor M2 becomes conductive to lower the intermediate potential VM. In this way, the intermediate potential VM is maintained within a range expressed as follows: EQU {VN1-(VTN1-VTN3)}&lt;VM&lt;{VN1+(VTP2-VTP4)} (4)
Thus, by setting the threshold voltage VTN1 larger than VTN3, and by setting VTN2 larger then VTP4, the intermediate potential VM is maintained within a range .DELTA.V as shown in FIG. 2. The range .DELTA.V is expressed as follows. EQU .DELTA.V=.DELTA.VTN+.DELTA.VTP (5)
wherein .DELTA.VTN (VTN1-VTN3), and .DELTA.VTP is (VTP2-VTP4).
In this way, the intermediate potential VM is maintained within a predetermined allowed range .DELTA.V. When the intermediate potential VM is within the range .DELTA.V, no through current flows between the terminal 6 and ground since both the MOS transistors M1 and M2 are nonconductive, and in the high impedance state. Thus, it is possible to employ MOS transistors of large dimension to increase the current driving capacity.
The constructions of FIGS. 1 (a) and (b) are simple. However, with these constructions it is impossible both to reduce power consumption and increase the driving capacity at the same time. Namely, in the case where a large capacitor is connected to the output terminals 2 and 4, a large current driving capacity is required to bring back the intermediate potential VM to the predetermined value determined by the resistance value, from the shifted potential level. When the resistance values of the resistors R1, R2 and R3 are reduced to increase the current driving capacity so as to obtain rapid recovery of the intermediate potential VM, the current which flows through the resistors increases, and the power consumption is increased.
In the prior are of FIG. 1 (c), by setting the resistance value of the resistors R4 and R5 sufficiently high, it is possible to reduce the power consumption. Furthermore, by increasing the dimension of the transistors M1 and M2, large current driving capacity is achieved.
However, the gate to source voltages of the MOS transistors M1 and M2 are difference voltages between the intermediate potential VM and the first and the second reference potentials VN2 and VN3. Therefore, in the condition where the intermediate potential VM is slightly out of the allowed range .DELTA.V, the transistors M1 and M2 operate in a saturation condition. Thus, the current driving capacities of the transistors M1 and M2 are not so large, as shown in FIG. 2, since the respective gate to source voltages supplied to the transistors are relatively small. Therefore, even if MOS transistors having large dimension are used for the MOS transistors M1 and M2 to increase the driving capacity, these transistors are not used effectively to increase the current driving capacity. Thus, the circuit of FIG. 1 (c) is inadequate in the case where fast response or rapid recovery is required.